[Lazarus] SdpoSerial Tx and Rx buffers?

[José Mejuto]

Hello Hans-Peter,

Thursday, February 17, 2011, 12:28:08 PM, you wrote:

>> the 16550A is interrupt driven and FIFO 16 bytes.
HPD> And the FIFO resides in the receiver, the transmitter doesn't have a
HPD> FIFO. At least it was so, 20 years ago...

Both have FIFOs, in fact the FIFO was implemented for the transmitter
(sender) to achive a speed higher than 38400 bps and before the chip
goes out a receive FIFO was added also.

Quote: --------------------

RBR : Receiver buffer register (RO) The RBR, receiver buffer register
contains the byte received if no FIFO is used, or the oldest unread
byte with FIFO's. If FIFO buffering is used, each new read action of
the register will return the next byte, until no more bytes are
present. Bit 0 in the LSR line status register can be used to check if
all received bytes have been read. This bit wil change to zero if no
more bytes are present.

THR : Transmitter holding register (WO) The THR, transmitter holding
register is used to buffer outgoing characters. If no FIFO buffering
is used, only one character can be stored. Otherwise the amount of
characters depends on the type of UART. Bit 5 in the LSR, line status
register can be used to check if new information must be written to
THR. The value 1 indicates that the register is empty. If FIFO
buffering is used, more than one character can be written to the
transmitter holding register when the bit signals an empty state.
There is no indication of the amount of bytes currently present in the
transmitter FIFO.
--------------------------

You can get further information from http://www.lammertbies.nl/comm/info/serial-uart.html

-- 
Best regards,
 José