[Lazarus] SdpoSerial Tx and Rx buffers?

[José Mejuto]

Hello Lazarus-List,

Thursday, February 17, 2011, 5:46:08 PM, you wrote:

>>AFAIK the FIFO is in the receive, in sent the FIFOs are filled but
>>function does not return until the hardware sends the last byte.
BB> At least in the embedded world UART:s have *both* a transmit and
BB> receive FIFO. You usually are able to set the interrupt trigger such
BB> that it fires when there are a certain number of bytes in the Rx FIFO
BB> and when it reduces below a certain number of bytes in the transmit
BB> FIFO. This way one can fill the FIFO with outgoing data and then go
BB> away doing something else until the iterrupt fires at which time the
BB> interrupt routine will move available data from the buffer to the
BB> FIFO.

Right, I do not correctly write the idea. I was trying to say that the
FIFO in acts like a buffer that you can forget about it (until no
receive event/interrupt) is received, while in the send FIFO the OS
waits for a full empty/transmission before return from call.

Are we completly off-topic ?

-- 
Best regards,
 José