[Lazarus] thread safe

[Michael Schnell]

On 06/28/2011 12:24 PM, Henry Vermaak wrote:
>
> To add to this, on x86 the memory barrier is probably implemented with 
> an atomic instruction.
>

Like MUTEX/FUTEX (and critical section) on the system level all this 
needs to be done using atomic (and with SMP bus locking / cache 
invalidating) instructions (with no-SMP, disabling the interrupt would 
be another system-level option).

-Michael